TSMC's progress on next-generation chip technology may be slower than expected. What does this mean for the AI chip industry chain?

TSMC's CoPoS mass production may be delayed until 2029, potentially forcing NVIDIA to adjust its chip design strategy and shift to alternative architectures.

According to news from the Wind Trading Platform, Nomura Securities' latest research shows that due to technical setbacks, TSMC's CoPoS packaging technology mass production timeline may be postponed from the originally planned 2027 to 2029-2030.

The report states that this delay may prompt NVIDIA to adopt a multi-chip module (MCM) architecture for its Rubin Ultra GPU, scheduled for release in 2027, similar to Amazon's Trainium 2 design, to circumvent the limitations of single module packaging.

For the AI industry chain, Nomura analyzes that TSMC may shift its 2026 chip backend capital expenditures to other technologies such as WMCM and SoIC, while CoWoS capacity allocation will become a key monitoring point.

Significant Delay in CoPoS Technology Forces NVIDIA to Adjust Product Roadmap

According to the report, CoPoS (chip-on-panel-on-substrate) technology aims to enhance area utilization through larger panel sizes (e.g., 310x310mm) to support the AI GPU demands of clients like NVIDIA.

However, Nomura's industry research indicates that TSMC's chip-level panel substrate packaging technology (CoPoS) development progress has significantly slowed. The originally planned mass production timeline for 2027 may be postponed to the second half of 2029.

This delay is primarily due to technological immaturity, especially in addressing key technical challenges such as handling panel and wafer discrepancies, controlling warpage over larger areas, and managing more redistribution layers (RDL).

The CoPoS delay will directly impact NVIDIA's product planning.

Nomura expects that NVIDIA's Rubin Ultra GPU, which was originally anticipated to require up to 8 wafer-sized CoWoS-L interconnects to integrate all chips and small chip stacks, may be forced to shift to an MCM architecture due to the CoPoS delay, distributing four Rubin GPUs across two modules connected via a substrate.

This adjustment is similar to Amazon AWS's Trainium 2, which uses CoWoS-R and MCM to place computing chips and HBM on organic interconnects, then onto a single substrate. Nomura Securities believes that such changes may help NVIDIA avoid delays, but could also increase design complexity and costs.

TSMC's Capital Expenditure Allocation Faces Adjustment

In terms of capacity, Nomura maintains its forecast for TSMC's CoWoS capacity, expecting it to reach 70,000 and 90,000-100,000 wafer monthly capacities by the end of 2025 and 2026, respectively.

At the level of 100,000 wafer monthly capacity, the report predicts that TSMC will not further advance the procurement of CoWoS capacity equipment but may achieve limited capacity growth through improved production efficiency.

With the delay in CoPoS mass production, TSMC's backend capital expenditures in 2026 (typically accounting for 10% of the total budget) may be more directed towards wafer-level multi-chip modules (WMCM) and system integrated chips (SoIC) technologies. The report warns that the market's expectations for WMCM may be overly optimistic, while expectations for SoIC are more conservative.

The report also lists several FOPLP equipment suppliers, including Zhisheng Industrial, Tianhong Technology, Youwei Technology, among others, covering process equipment from carrier bonding to automated optical inspection. Nomura believes these companies may benefit from CoPoS-related investments, but technological delays could also postpone their equipment demand